The present invention relates to a phase-lock loop (PLL), and more particularly, to a PLL with independent phase and frequency adjustment circuits that may be used in synchronous memory devices.
An external signal supplied to an electrical system is inevitably corrupted by additive noise. For various applications, such as clock generation, a highly stable signal is required. Therefore, the external signal should be processed to remove as much noise as possible.
To produce a stable internal signal based on the external signal, a conventional PLL may employ a current-controlled oscillator (CCO), whose frequency is controlled by a control current. A phase detector compares the phase of the external signal against the phase of the CCO output to determine an error signal that indicates the phase difference. To suppress noise, the error signal is averaged over some length of time, and the average value is used to produce the control current applied to the CCO to change its frequency in a direction that reduces the phase difference between the input signal and the CCO output.
Referring to FIG. 1, a conventional PLL 30 for producing a highly accurate internal clock INT.CLK based on an external reference clock EXT.CLK may comprise a phase detector 32 supplied with the EXT.CLK signal. Via a charge pump 34, a loop filter 36, and a voltage-to-current transformer 38, the output of the phase detector 32 is coupled to a control input of a CCO 40. A level shifting and buffering circuit 42 coupled to the CCO output produces the INT.CLK signal supplied via a feedback loop to the phase detector 32.
The phase detector 32 compares the phase "PHgr"int of the INT.CLK signal with the phase "PHgr"ext of the EXT.CLK signal to generate a phase error voltage Vd=Kc("PHgr"extxe2x88x92"PHgr"int), where Kc is called the phase detector gain factor and is measured in units of volts per radian. The gain factor Kc is determined by the charge pump 34 used to charge and discharge the loop filter 36.
The phase error voltage Vd is filtered by the loop filter 36 that suppresses noise and high-frequency components of the phase error signal. The voltage-to-current transformer 38 converts the filtered phase error voltage into control current that defines the frequency of the CCO 40. The level shifting and buffering circuit 42 translates the level of the CCO output into a level required for a system supplied with the INT.CLK signal, and provides an interface between the PLL and this system.
When the loop is locked, the control current is such that the frequency of the CCO is equal to the average frequency of the EXT.CLK signal. For each cycle of the EXT.CLK signal there is one, and only one, cycle of the CCO output. To maintain the control current needed for lock, it is generally necessary to have a nonzero output from the phase detector. Consequently, the loop operates with some phase error present.
Since frequency is the derivative of phase, a conventional PLL performs frequency adjustment of an incoming signal simultaneously with adjustment of its phase. The frequency and phase adjustments are carried out using the phase detector 32 which performs phase comparison at the frequency of the CCO output signal supplied via the feedback loop. The error signal at the output of the phase detector 32 indicates instantaneous phase difference. The loop filter 36 provides averaging of the error signal over some time interval to establish an average value used for producing the control current applied to the CCO 40. Deviation of the CCO from its center frequency caused by the control current may be described as d"PHgr"0/dt, where "PHgr"0 is the phase of the CCO output equal to the phase "PHgr"int of the INT.CLK signal produced by the PLL 30. In other words, a conventional PLL performs frequency and phase adjustments in the same loop.
A PLL starts out in an unlocked condition and must be brought into lock. The process of bringing a conventional PLL into lock is often a slow and unreliable process performed by the phase detector 32 that tracks variations of the INT.CLK signal with respect to the reference EXT.CLK signal. In particular, when the INT.CLK signal leads in phase with respect to the EXT.CLK signal, or the frequency of the INT.CLK signal is higher than the frequency of the EXT.CLK signal, the phase detector 32 causes the charge pump 34 to increase the potential at the output of the loop filter 36. In response, the voltage-to-current transformer 38 reduces the value of the control current applied to the CCO 40. As a result, the frequency of the INT.CLK signal at the output of the CCO 40 reduces. The reduction of the INT.CLK frequency causes the delay of the INT.CLK signal to reduce its phase lead with respect to the EXT.CLK signal.
By contrast, when the INT.CLK signal lags in phase with respect to the EXT.CLK signal, or the frequency of the INT.CLK signal is lower than the frequency of the EXT.CLK signal, the phase detector 32 causes the charge pump 34 to reduce the potential at the output of the loop filter 36. In response, the voltage-to-current transformer 38 increases the value of the control current applied to the CCO 40. When the control current increases, the frequency of the INT.CLK signal at the output of the CCO 40 increases. The INT.CLK frequency increase causes the INT.CLK signal to reduce its phase lag with respect to the EXT.CLK signal.
However, in conventional PLLs, it takes a long time to reach a locked state when the frequency of the INT.CLK signal becomes close to the frequency of the EXT.CLK signal. It would be desirable to provide a PLL that reduces the time required to bring the loop into a locked state.
If the INT.CLK frequency is close enough to the EXT.CLK frequency, a conventional PLL locks up with just a phase transient. There is no cycle slipping prior to lock. It would be desirable to provide a PLL that operates in a wide frequency range over which the loop could be brought into a locked state without slipping cycles.
A small phase error enables a PLL to maintain a locked state. However, if the error becomes so large that the CCO skips cycles, the PLL is considered to have lost lock. A recovery time is required to acquire lock again. It would be desirable to provide a PLL that requires a short recovery time.
Accordingly, one advantage of the present invention is in providing a PLL that reduces the time required to bring its loop into a locked state, compared to a conventional PLL.
Another advantage of the present invention is in providing a PLL that operates in a wide frequency range over which its loop can be brought into a locked state without slipping cycles.
A further advantage of the present invention is in providing a PLL that requires a short recovery time.
The above and other advantages of the invention are achieved, at least, in part, by providing a system for generating an internal clock signal in response to an external clock signal. The system comprises a phase adjustment circuit responsive to the external clock signal and the internal clock signal for producing a phase adjustment signal that represents difference between the phase of the external clock signal and the phase of the internal clock signal. A frequency adjustment circuit is responsive to the external clock signal and the internal clock signal for producing a frequency adjustment signal that represents difference between the frequency of the external clock signal and the frequency of the internal clock signal. A control value calculator is responsive to the phase adjustment signal and the frequency adjustment signal for producing a resulting control signal supplied to a signal-controlled oscillator that generates the internal clock signal at an internal clock frequency deviating in response to the resulting control signal.
In accordance with a first embodiment of the present invention, the frequency adjustment circuit may comprise a frequency detector responsive to the external and internal clock signals for producing an instantaneous value of a frequency error signal that indicates difference between instantaneous frequencies of the internal clock signal and the external clock signal. An accumulator may be coupled to the frequency detector for accumulating instantaneous values of the frequency error signal over a preset time period to produce an accumulated signal that indicates an average value of the frequency difference for the preset time period. An adjusting circuit may be coupled to the accumulator for adjusting the accumulated signal to produce the frequency adjustment signal.
In accordance with another embodiment of the present invention, the frequency adjustment circuit may comprise a first counter responsive to the external clock signal and the internal clock signal for counting the number of periods of the external clock signal in a half cycle of the internal clock signal in which the internal dock signal is at a first logic level. A second counter may count the number of periods of the external clock signal in a half cycle of the internal clock signal in which the internal clock signal is at a second logic level. A third counter may count the number of periods of the internal clock signal in a half cycle of the external clock signal in which the external clock signal is at the first logic level. Finally, a fourth counter may count the number of periods of the internal clock signal in a half cycle of the external clock signal in which the external clock signal is at the second logic level.
First, second, third and fourth adders may be respectively coupled to the first, second, third and fourth counters for accumulating n-bit counts produced by the first, second, third and fourth counters to generate m-bit accumulated values. First, second, third and fourth decoders may be respectively coupled to the first, second, third and fourth adders to generate first, second, third and fourth frequency control values supplied, together with a base value representing the phase adjustment signal, to the control value calculator. In response, the control value calculator may add the first or second frequency control values to the base value, or subtract the third or fourth frequency control values from the base value.
A reference current generator may be provided for supplying the first, second, third and fourth decoders with reference current to present the first, second, third and fourth frequency control values as first, second, third and fourth frequency control currents. The base value may be represented by base current. In response to the first, second, third and fourth frequency control currents and the base current, the control value calculator may produce the resulting control current supplied to the signal-control oscillator to adjust frequency and phase of the internal clock signal.
In accordance with a further embodiment of the present invention, the frequency adjustment circuit may comprise a first frequency divider supplied with the internal clock signal for producing a divided internal clock signal at a frequency equal to the frequency of the internal clock signal divided by a preset number. A second frequency divider may be supplied with the external clock signal for producing a divided external clock signal at a frequency equal to the frequency of the external clock signal divided by the preset number.
A first counter may be coupled to the first frequency divider and supplied with the external clock signal for counting the number of periods of the external clock signal in a half cycle of the divided internal clock signal. A second counter may be coupled to the second frequency divider and supplied with the internal clock signal for counting the number of periods of the internal dock signal in a half cycle of the divided external clock signal.
First and second adders may be respectively coupled to the first and second counters for accumulating n-bit counts produced by the first and second counters to generate m-bit accumulated values. First and second decoders may be respectively coupled to the first and second adders to generate first and second frequency control values supplied to the control value calculator In response, the control value calculator may add the first frequency control value to the base value, or subtract the second frequency control value from the base value.
In accordance with another embodiment of the present invention, a fine adjustment circuit may be provided for fine frequency tuning of the signal-controlled oscillator, in addition to rough frequency adjustment carried out by the frequency adjustment circuit, and phase adjustment provided by the phase adjustment circuit. The fine adjustment circuit may comprise a delay monitor for delaying the external clock signal by a delay amount defined by a period of the signal-controlled oscillator. A comparator may compare a delayed external clock signal produced by the delay monitor with the external clock signal to generate a fine control signal supplied to the control value calculator to modify the resulting control signal.
In accordance with a further embodiment of the present invention, the fine adjustment circuit may comprise a delay model responsive to the external clock signal for producing a first output signal delayed by a first delay time smaller than a period of the signal-controlled oscillator, and for producing a second output signal delayed by a second delay time larger than the period of the signal-controlled oscillator.
A logic circuit may be coupled to the delay model and supplied with an input signal to the delay model for determining logic levels of the first and second output signals when the input signal goes from a first level to a second level. The logic circuit may produce a down signal when both the first and second output signals are at the first level. An up signal may be produced when both the first and second output signals are at the second level when said input signal goes from the first level to the second level. The control value calculator may increase a value of the resulting control signal in response to the up signal, or decrease the value of the resulting control signal in response to the down signal.
A frequency divider may be coupled to the delay model for producing its input signal at a frequency equal to the frequency of the external clock signal divided by a predetermined amount.
A first adder may be coupled to the logic circuit for accumulating instantaneous values of the up signal to generate an m-bit accumulated value of the up signal. A second adder may be coupled to the logic circuit for accumulating instantaneous values of the down signal to generate an m-bit accumulated value of the down signal. First and second decoders may be respectively coupled to the first and second adders to generate first and second fine tuning values supplied to the control value calculator. In response, the control value calculator may add the first fine tuning value to the base value, or subtract the second fine tuning values from the base value.
The signal-controlled oscillator may comprise a ring oscillator having k serially connected inverter stages, where k is an odd number. The delay model may comprise more than 2k serially connected delay stages similar to the inverter stages in the ring oscillator. The first output signal may be produced at an output of delay stage 2kxe2x88x92l, where l is an integer. For example, l may equal to 1. The second output signal may be produced at an output of delay stage 2k+l.
Also, the fine adjustment circuit may comprise a reference current generator for supplying the first and second decoders with reference current to present the first and second fine tuning values as first and second fine tuning currents. The control value calculator may produce resulting control current supplied to the ring oscillator to tune its frequency.
In accordance with a method of the present invention, to produce an internal clock signal in synchronism with an external clock signal, the following steps are carried out:
comparing phase of the internal clock signal with phase of the external clock signal to produce a phase adjustment signal representing differences in phase and frequency between the internal clock signal and the external clock signal,
comparing frequency of the internal clock signal with frequency of the external clock signal independently from the step of phase comparing, to produce a frequency adjustment signal representing difference between the frequency of the internal clock signal and the frequency of the external clock signal,
producing a control signal representing the phase adjustment signal and the frequency adjustment signal, and
controlling a signal-controlled oscillator by the control signal to produce the internal control signal synchronized with the external control signal.
The steps of phase comparing and frequency comparing may be carried out by separate circuits.
Further, fine tuning of the signal-controlled oscillator may be carried out when the frequency of the internal clock signal is close to the frequency of the external clock signal. The step of fine tuning may comprise the step of delaying the external clock signal by a delay time defined by a period of the signal-controlled oscillator. A delayed external clock signal may be compared with the external clock signal to produce a fine tuning signal. The resulting control signal may be produced so as to represent the phase adjustment signal, the frequency adjustment signal and the fine tuning signal.
In accordance with another aspect of the present invention, a memory device supplied with an external clock signal comprises:
a memory cell array for storing data, and
an internal synchronous clock signal generator responsive to the external dock signal for producing an internal clock signal supplied to internal circuits of the memory device to control various data reading and writing operations.
The internal synchronous clock signal generator includes:
a phase adjustment circuit responsive to the external clock signal and the internal clock signal for producing a phase adjustment signal representing difference between phase of the external clock signal and phase of the internal dock signal,
a frequency adjustment circuit responsive to the external clock signal and the internal clock signal for producing a frequency adjustment signal representing difference between frequency of the external clock signal and frequency of the internal clock signal,
a control value calculator responsive to the phase adjustment signal and the frequency adjustment signal for producing a resulting control signal, and
a signal-controlled oscillator responsive to the resulting control signal for supplying the internal circuits with the internal clock signal modified in response to the resulting control signal.
Still other advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.